module id_exe(
    input clk,
    input reset,
    input [5:0] stall,

    input i_write_to_mem,
    input i_write_to_regfile,
    input [4:0] i_reg_addr,
    input [16:0] i_ALUControl,
    input [63:0] i_sext_imm,
    input i_aluimm,
    input [63:0] i_data1,
    input [63:0] i_data2,
    input i_is_jump,
    input [3:0] i_mem_control,
    input i_mem_to_regfile,
    input [63:0] i_pc,
    input [31:0] i_inst,
    input [11:0] i_csr,
    input [63:0] i_csr_wdata,
    input [2:0] i_csr_control,
    input [63:0] i_badvaddr,
    input [63:0] i_excode,
    input i_except_ena,
    input flush,
    input i_ret,
    input i_inst_r_valid,
    input i_shift,
    input [63:0] i_shamt_ext,

    output reg o_write_to_mem,
    output reg o_write_to_regfile,
    output reg [4:0] o_reg_addr, //回到control_unit
    output reg [16:0] o_ALUControl,
    output reg [63:0] o_sext_imm,
    output reg o_aluimm,
    output reg [63:0] o_data1,
    output reg [63:0] o_data2,
    output reg o_is_jump,
    output reg [3:0] o_mem_control,
    output reg o_mem_to_regfile,
    output reg [63:0] o_pc,
    output reg [31:0] o_inst,
    output reg [11:0] o_csr,
    output reg [63:0] o_csr_wdata,
    output reg [2:0] o_csr_control,
    output reg [63:0] o_badvaddr,
    output reg [63:0] o_excode,
    output reg o_except_ena,
    output reg o_ret,
    output reg o_inst_r_valid,
    output reg o_shift,
    output reg [63:0] o_shamt_ext
);

    always@(posedge clk) begin
        if(reset) begin
            o_write_to_mem <= 1'b0;
            o_write_to_regfile <= 1'b0;
            o_reg_addr <= 5'd0;
            o_ALUControl <= 17'd0;
            o_sext_imm <= 64'd0;
            o_aluimm <= 1'b0;
            o_data1 <= 64'd0;
            o_data2 <= 64'd0;
            o_is_jump <= 1'b0;
            o_mem_control <= 4'b0000;
            o_mem_to_regfile <= 1'b0;
            o_csr <= 12'd0;
            o_csr_wdata <= 63'd0;
            o_csr_control <= 3'b000;
            o_badvaddr <= 64'd0;
            o_excode <= 64'd0;
            o_except_ena <= 1'b0;
            o_ret <= 1'b0;
            o_inst_r_valid <= 1'b0;
            o_shift <= 1'b0;
            o_shamt_ext <= 64'd0;
        end else if(flush) begin
            o_write_to_mem <= 1'b0;
            o_write_to_regfile <= 1'b0;
            o_reg_addr <= 5'd0;
            o_ALUControl <= 17'd0;
            o_sext_imm <= 64'd0;
            o_aluimm <= 1'b0;
            o_data1 <= 64'd0;
            o_data2 <= 64'd0;
            o_is_jump <= 1'b0;
            o_mem_control <= 4'b0000;
            o_mem_to_regfile <= 1'b0;
            o_csr <= 12'd0;
            o_csr_wdata <= 63'd0;
            o_csr_control <= 3'b000;
            o_badvaddr <= 64'd0;
            o_excode <= 64'd0;
            o_except_ena <= 1'b0;
            o_ret <= 1'b0;
            o_inst_r_valid <= 1'b0;
            o_shift <= 1'b0;
            o_shamt_ext <= 64'd0;
        end else if(stall[2] == 1'b1 && stall[3] == 1'b0) begin
            o_write_to_mem <= 1'b0;
            o_write_to_regfile <= 1'b0;
            o_reg_addr <= 5'd0;
            o_ALUControl <= 17'd0;
            o_sext_imm <= 64'd0;
            o_aluimm <= 1'b0;
            o_data1 <= 64'd0;
            o_data2 <= 64'd0;
            o_is_jump <= 1'b0;
            o_mem_control <= 4'b0000;
            o_mem_to_regfile <= 1'b0;
            o_csr <= 12'd0;
            o_csr_wdata <= 63'd0;
            o_csr_control <= 3'b000;
            o_badvaddr <= 64'd0;
            o_excode <= 64'd0;
            o_except_ena <= 1'b0;
            o_ret <= 1'b0;
            o_inst_r_valid <= 1'b0;
            o_shift <= 1'b0;
            o_shamt_ext <= 64'd0;
        end else if(stall[2] == 1'b0 && stall[3] == 1'b0) begin
            o_write_to_mem <= i_write_to_mem;
            o_write_to_regfile <= i_write_to_regfile;
            o_reg_addr <= i_reg_addr;
            o_ALUControl <= i_ALUControl;
            o_sext_imm <= i_sext_imm;
            o_aluimm <= i_aluimm;
            o_data1 <= i_data1;
            o_data2 <= i_data2;
            o_is_jump <= i_is_jump;
            o_mem_control <= i_mem_control;
            o_mem_to_regfile <= i_mem_to_regfile;
            o_csr <= i_csr;
            o_csr_wdata <= i_csr_wdata;
            o_csr_control <= i_csr_control;
            o_badvaddr <= i_badvaddr;
            o_excode <= i_excode;
            o_except_ena <= i_except_ena;
            o_ret <= i_ret;
            o_inst_r_valid <= i_inst_r_valid;
            o_shift <= i_shift;
            o_shamt_ext <= i_shamt_ext;
        end
    end

    always@(posedge clk) begin
        if(reset) begin
            o_pc <= 64'h0000000080000000;
            o_inst <= 32'd0;
        end else if(stall[2] == 1'b0 && stall[3] == 1'b0) begin
            o_pc <= i_pc;
            o_inst <= i_inst;
        end
    end

endmodule
